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ASTRA’S SCORECARD

Hairpin A1

@chih-yang04·2 copper layers·USB-programmable coin-cell OLED wearable prototype·moderate complexity·On the leaderboard

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ASTRA SCORE
70/100
TOASTEDLIGHTLY TOASTED
LIGHTLY TOASTED
ASTRAHAS ENTERED THE CHAT
The OLED boost switch node takes 14 mm and two vias to connect three parts. Apparently even a hairpin needs a scenic route.

A well-documented, DRC-clean OLED prototype with sensible interfaces, but power-loop layout needs refinement and wearable release remains unqualified.

THE BREAKDOWN20% EACH
Routing77/100

Complete two-layer routing and filled ground pours provide a solid baseline. USB data nets are short at roughly 18 mm each; impedance and local return continuity are not established by these measurements.

Power integrity60/100

USB regulation, source selection and a default-off OLED boost form a sensible architecture. Switching-node geometry and remote bypass capacitors undermine the implementation; coin-cell operation still depends on a restricted display duty cycle.

Circuit design & placement77/100

The front is reserved for the display and edge USB connector, with support electronics behind it. Separate CC resistors, defined boot/reset biasing and accessible service-pad grouping show coherent interface design.

Manufacturability77/100

Clean configured DRC, 0.3 mm through-via drills and dedicated service pads are practical positives. Custom OLED attachment and battery-contact details still require the sample checks explicitly identified in the design record.

Clarity & silkscreen70/100

Detailed rationale and bring-up documentation compensate for a deliberately sparse board. All 35 reference fields are hidden, making component identification during rework dependent on external documentation.

FIX THESE FIRST
01

The boost power stage needs a tighter layout

The /SW net connects U5, L1 and D1 through 14.23 mm of track and two vias despite all three parts being on the back. This is an unnecessarily extended fast-switching node, adding parasitic inductance and coupling exposure; ringing or malfunction has not been measured.

Fix: Cluster U5, L1, D1 and the input/output capacitors; keep the switch node short on one layer and minimize the switched-current return loop.

02

Put bypass capacitors at their consumers

The saved minimum pad-distance measurements place C2 about 9.06 mm from U2 and the MCU's 100 nF capacitors C5/C6 about 6.91/4.80 mm from U4. These are connected supply capacitors, but their placement leaves avoidable connection inductance; the figures are not routed loop lengths.

Fix: Move C2 beside the LDO output and place one 100 nF capacitor directly beside each MCU supply pin with a short ground return.

03

Keep custom mechanical interfaces behind the prototype gate

The design record explicitly leaves OLED contact side, pad dimensions, flex bend/support and battery-contact finish validation open. A clean courtyard check cannot establish these physical interfaces fit.

Fix: Validate the display and retainer against physical samples, then freeze attachment geometry and contact finish before an assembly order.

04

Restore a small service-oriented reference legend

Every source reference field is hidden. That preserves the display-focused appearance, but makes locating individual back-side parts during debug less convenient.

Fix: Expose selected back-side references around the power stage and service pads, or provide a clearly indexed assembly drawing.

What works

  • Configured DRC, unconnected-item and schematic-parity checks report zero violations.
  • Separate USB-C CC pulldowns, USB ESD protection and six SWD/DFU service pads support practical bring-up.
  • The design record explicitly documents battery-load assumptions, mechanical uncertainties and a useful prototype test sequence.

Review scope

This review assesses design evidence. Physical testing and manufacturing validation are outside its scope.

7 coverage notes
  • PCB layer images were unavailable for this version.
  • The copper graph tool was unavailable; routing assessment used saved CAD measurements and a partial source-segment inspection, not a full return-path audit.
  • Current ERC reports 69 library-configuration warnings and no errors; these do not establish incorrect symbols or footprints.
  • No measured boost waveforms, USB performance, battery sag or runtime were provided. The documented 25–50 mA example is an estimate, not an operating measurement.
  • Firmware, enclosed battery retention and clip integration remain explicitly unfinished prototype work; this review does not certify wearable safety.
  • No fabrication-house profile or physical assembly validation was available.
  • Some automated schematic checks were unavailable: symbol pins, drawing layout, no-connect markers, component descriptions.