“J2 has a reversible USB-C shell and one-sided data wiring. The connector offers two orientations; the circuit has a favourite.”
Not ready for fabrication: USB data wiring needs correction, and the via and fine-pitch footprint geometry need a manufacturing cleanup. The power architecture also needs an explicit charging-use policy.
Outer-layer routing is complete against the netlist, but the USB interface contains a functional connectivity omission. The flagged 0.15 mm signal widths alone are not defects.
Power pours and local bypass/bulk capacitors provide a reasonable foundation. The battery-fed LDO architecture needs charging-mode and low-battery operating limits established before wearable use.
The amplifier and charger have nearby support capacitors. Module bypassing is less tight: C6 and C3 measure 4.62 mm and 7.06 mm from shared supply/ground pads; closer placement would improve the layout margin.
The configured DRC reports 43 errors, including concrete via-size, annular-ring, mask and clearance violations. These need resolution against an agreed process, not blanket waivers.
All 54 reference fields are enabled on silkscreen, but numerous references overlap clearance regions or are clipped by solder mask. The labeling needs a fabrication-output cleanup.
USB-C's second data-contact pair is left disconnected
J2 A6/A7 connect to USB+/USB-, while B6/B7 remain on separate unconnected nets and distinct PCB pads. With the specified 16-pin receptacle, this leaves USB data unavailable in one plug orientation.
Fix: Join A6 to B6 and A7 to B7 near J2, then route the resulting pair and test enumeration in both orientations.
Six through-vias violate the board's own annular-ring rules
Six vias use 0.30 mm copper diameter with 0.20 mm drills, leaving 0.05 mm annular rings. KiCad requires at least 0.10 mm rings and 0.50 mm via diameter in this project's setup; these are actual rule violations, not merely generic detector preferences.
Fix: Enlarge these vias to satisfy the configured rules, or obtain explicit fabricator approval and encode the approved process limits.
U4's fine-pitch land pattern needs mask and clearance reconciliation
KiCad reports front-mask apertures bridging different nets at U4 and 0.155 mm copper spacing against a 0.200 mm requirement. This does not prove the custom footprint is electrically wrong, but its geometry is incompatible with the current rules.
Fix: Check U4's land pattern against its package drawing and the assembler's mask-web limits; adjust pads, mask openings or justified local rules, then rerun DRC.
Operating while charging puts the system load on the charger output
U3's battery output feeds BAT_IN, which SW3 connects directly to SYS_PWR when on. Without a separate load-sharing path, system current contributes to the MCP73831's sensed charging current and can prevent charge termination; this matters if operation during charging is intended.
Fix: Add a power-path/load-sharing circuit, or enforce and document charging with SW3 off.
Reference text will be clipped in fabrication
Stored DRC identifies solder-mask clipping of reference fields including R17, D3, C3 and C6, alongside numerous silk-clearance overlaps. Enabled text is not necessarily readable text on the finished board.
Fix: Move or selectively suppress conflicting silk references while retaining assembly documentation, then inspect the exported silk against mask openings.
What works
- The four-layer layout includes a filled ground plane and dedicated inner-layer power pours.
- USB-C CC1 and CC2 each have their own 5.1 kΩ pull-down.
- KiCad reports zero unrouted connections and zero schematic–PCB parity violations; the intended netlist is implemented consistently.
Review scope
This review assesses design evidence. Physical testing and manufacturing validation are outside its scope.
5 coverage notes
- No battery specification, motor current, load profile or enclosure was provided; runtime, regulator thermal/dropout margin and battery protection were not validated.
- USB impedance, detailed return paths and RF performance were not simulated or measured.
- No fabricator profile was selected. Other reported U2 and switch clearance/keepout violations remain to be reconciled; they are not treated here as proven shorts or RF failures.
- ERC includes undriven-power declarations, unused pins and unavailable-library warnings; these were not counted as evidence that the physical supplies or footprints are wrong.
- Some automated schematic checks were unavailable: symbol pins, drawing layout, no-connect markers, component descriptions.