“The USB-to-serial chip sits over 50 mm from its connector. Even a business card has apparently discovered the commuter lifestyle.”
A coherent interactive name card, but not fabrication-ready under its configured rules. Resolve the USB connector footprint errors and strengthen supply decoupling before release.
Two-layer routing uses conventional 0.2–0.5 mm traces and 0.6/0.3 mm vias, with no unconnected items reported. USB has one transition per signal; return-path continuity and impedance remain unverified.
USB VBUS genuinely supplies +5V, despite the source-detection warning. Local 100 nF bypassing is present, but reservoir capacitance and separate MCU supply-pin decoupling deserve improvement.
The regular front-panel grid and nearby expander bypass capacitors are sensible. The USB bridge is unnecessarily distant from the connector for this board's size.
Ordinary packages and via dimensions keep fabrication approachable, but four configured DRC errors remain in USBC1. These need footprint corrections or documented process approval, not blanket waivers.
Name, game title and RESET text support the card's purpose; hiding front-side references is a reasonable aesthetic choice. Repeated connector and LED outline clearance warnings weaken the finishing quality.
Resolve USB connector pad and hole definitions
USBC1 has two different-net clearances of about 0.100 mm against the configured 0.127 mm rule. Its two unnumbered holes are classified as plated, with DRC reporting zero annular ring against a 0.075 mm minimum.
Fix: Check the connector drawing: make locating holes NPTH if appropriate, and revise the custom pads or obtain explicit fabrication approval for their spacing.
Give the supply more local energy storage
The +5V rail has four 100 nF capacitors and no larger reservoir capacitor. U3 has two VCC pins plus AVCC, but only C3 is locally placed; the next +5V bypass candidate is 8.07 mm away and sits beside U1. This leaves transient margin dependent on shared routing and the USB source.
Fix: Add modest USB-compatible bulk capacitance and local bypassing at U3's distinct supply-pin groups, keeping each ground loop short.
Move the USB bridge toward the connector
U5 and USBC1 are over 50 mm apart. The USB nets contain 60.96 mm and 64.20 mm of total routed copper, including connector branches; this is avoidable length, not proof of a full-speed USB failure or a measured pair skew.
Fix: Place U5 nearer USBC1 and route the USB pair together over continuous ground, leaving the longer run to the UART.
Trim footprint outlines away from solder-mask openings
Stored DRC reports repeated silk-to-mask clearance violations around the LEDs and USB connector; LED6 examples reach 0.065 mm against the configured 0.150 mm requirement. Fabrication clipping can remove parts of these outlines.
Fix: Simplify the LED and connector silk graphics to meet the chosen process clearance, then inspect the final clipped silkscreen output.
What works
- The 17 mm button grid and consistently offset LEDs give the game a deliberate, usable layout.
- Both USB-C CC pins have separate 5.1 kΩ pull-downs, and the UART transmit/receive connections are correctly crossed.
- Six dedicated pads expose the programming signals, reset, power and ground; stored DRC reports no unrouted connections.
Review scope
This review assesses design evidence. Physical testing and manufacturing validation are outside its scope.
6 coverage notes
- No firmware, USB compliance testing, transient measurements or final fabrication order was available; operation and production yield are not established.
- Copper lengths are net totals, not endpoint timing measurements; detailed USB coupling, impedance and return paths were not evaluated.
- ERC ran with seven errors, including power-source declarations and unused U4 pins. Library-configuration warnings do not establish incorrect components.
- The configured rules carry JLCPCB names but were not independently validated against a current fabrication tier. Two courtyard-related checks were ignored.
- QR-code scanability, printed appearance and connector mating mechanics were not physically tested.
- Some automated schematic checks were unavailable: symbol pins, drawing layout, no-connect markers, component descriptions.