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MNT Reform LS1028A SoM

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mntre/ls1028a-som

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Source package

Original hardware design source archive

Original project source73 MB

Fabrication package

Gerbers and drill, pick-and-place, DRC report, and the 3D model

Gerbers and drill zip110 KBGerbers and drill zip: reform-edp-flex24 KBPick and place (CSV)566 BPick and place (CSV): reform-edp-flex158 B3D board only (GLB)2.8 MB

Review package

Schematics, PCB views, BOM, and extracted files

Schematic PDF78 KBSchematic, reform2-ls1028a-edp-adapter sheet364 KBSchematic, reform-edp-flex sheet132 KBPCB SVG161 KBPCB SVG: reform-edp-flex103 KB

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README

MNT Reform Layerscape LS1028A SoM

MNT Reform Layerscape LS1028A SoM Render

This is the open hardware system-on-module featuring the NXP Layerscape LS1028A processor and 16GB of DDR4 RAM. It can be used in the MNT Reform open hardware laptop or in any other custom device.

The module was designed by RBZ Embedded Logics in collaboration with MNT Research.

Status

The first production version of the module (rev02b, see below) runs Linux and is fully validated and integrated with MNT Reform.

The design is made in Altium. The free and open source EDA suite KiCAD version 6 can import these files for inspection and editing.

You can manufacture the module yourself or acquire it here:

Specs

  • System-on-Chip: NXP LS1028A
  • CPU: 2x ARM Cortex-A72 (1.5GHz, 1MB L2, 48KB L1I, 32KB L1D, ECC, Cache Coherent Interconnect CCI-400)
  • GPU: Vivante GC7000L (open source etnaviv drivers in Linux kernel), ARM eDP Controller
  • Memory: 16GB DDR4
  • 2x PCIe 3.0 (1x external PCIe 3.0 routed to HDMI pins)
  • SATA 3
  • 2x USB 3.0
  • 1GBit Ethernet w/ Marvell Alaska PHY
  • SAI audio
  • eMMC (size TBD), QSPI flash, EEPROM
  • SD, UART, SPI, I2C, PWM, GPIO
  • Powered by single 5V input

MNT Reform Layerscape LS1028A SoM Schematics Overview

Firmware/Software

Rev02b Changes

  • The 9 level shifters (NXB0104BQX) had the wrong footprints. This has been corrected.
  • The intented BOOTCFG mechanism via level shifter D6 does not work, so we remove it in production and connect the three CFG_RCW_SRC0..2 pins to GND to select SD card boot.

Rev01 Changes

Schematics:

  • 2x 49R9 pull-down resistors added in the outputs of G5, before decoupling caps.
  • Level shifting voltage translators ref. TXS0108ERGYR changed to NXB0104BQX.
  • NXB0104BQX voltage translators added to isolate CFG_RCW_SRC[2..0] from UART1.TX and UART2.TX in boot-up procedure.
  • D12 power rail connected to 3V3, instead of 1V2.
  • TA_TMP_DETECT pin connected to +VDD.
  • I2C voltage translator added to I2C1.

PCB:

  • DDR4 footprint modified to match 10.5mm x 13mm x 1.2mm dimensions.
  • Manufacturing notes added to the PCB.

All hardware design work in this repository is © 2021 RBZ Embedded Logics / RBZ Robot Design S.L., Madrid, Spain. The module was designed in collaboration with MNT Research GmbH, Berlin, Germany, who are hosting the repository.

License

All hardware sources are licensed under the CERN Open Hardware Licence Version 2 - Strongly Reciprocal.

Funding

NLNet logo

This project receives funding by NLNet.

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