Great care was taken during the PCB routing phase to minimize radiated and conducted emissions:

• 4-Layer Stackup: Allows for smaller L1-to-L2 distances, increasing plane coupling and reducing radiated emissions.
• Strategic Placement: The MLCC capacitors "hug" the MOSFETs on the input and the inductors on the output to minimize high-frequency current return paths. The slower bulk electrolytic capacitors are placed further out at the input/output terminals.
• Node Optimization: The physical copper area of the noisy switching (SW) nodes was kept to an absolute minimum. Molded inductors were chosen specifically to further contain magnetic emissions.
• Signal Isolation: Delicate analog feedback signals for the current loops were routed exclusively on the bottom layer to shield them from the noisy power stage on the top layer. They were also routed as differential pairs in order to minimise common mode noise.

The Digital Stage & UI

The control circuitry relies heavily on the STM32G474's internal mixed-signal capabilities. Additionally, the system features a local user interface: a rotary encoder is connected to a hardware timer in encoder mode, allowing the user to adjust voltage and current setpoints on the fly, which are displayed on an integrated 16x2 LCD.

Control Loop Architecture

The core of the project is its dual-loop control scheme, leveraging the specific hardware accelerators of the STM32G4 family:

1. Software Voltage Control Loop

• Averaged Sampling: The High-Resolution Timer (HRTIM) triggers ADC3 to sample the feedback voltage (buffered via an internal OpAmp) at the exact midpoint of the MOSFET's on-time. This effectively averages the signal without requiring software filtering.
• Hardware Math Acceleration: The ADC value is sent via DMA directly to the Filter Math Accelerator (FMAC) WDATA register, where a Proportional (P) control algorithm is calculated in hardware.
• Duty Cycle Update: Once the FMAC presents the result in the RDATA register, it generates an interrupt. The MCU core wakes up, applies corrections for phase current mismatch, and writes the new duty cycle to the HRTIM CMP1xR register.

2. Hardware Current Control Loop

• Differential Measurement: Current is measured via a shunt resistor at the low-side source. The small signal is read differentially for improved noise rejection.
• Internal Analog Processing: The voltage is amplified by an internal MCU difference amplifier and immediately fed into a built-in hardware comparator against a threshold set by an internal DAC.
• Asynchronous Shutdown: The comparator output is routed directly to the HRTIM external event port. This asynchronous link ensures near-zero latency between an overcurrent event and power stage shutoff, effectively realizing valley current control mode.
• Blanking Window: The HRTIM utilizes an internal event blanking window to ignore switching transients, preventing false safety triggers.

Results & Verification

Testing was conducted in progressive stages to ensure system stability and safety:

1. Controller Verification (No Power Stage): Feedback voltages were injected directly into the digital section to validate the software. Interleaving, dead-time insertion, duty cycle adjustment, soft start, current balancing, and overcurrent protection were all verified before high voltage was applied.

2. Real-World Ripple Testing: With the power stage assembled and hooked to a 25V lab supply, the output voltage ripple was measured at no load.

The dual-phase interleaved topology yielded a voltage ripple of just 7mVp-p. Compared to single-phase operation (which measured 35mVp-p), interleaving provided an 80% reduction in ripple purely through topology.

3. Efficiency Analysis: The converter was tested across its full operating range using an electronic DC load.

Test conditions note: Testing was capped at 25V input (instead of 30V) due to observed ringing at the switching node, which threatened to exceed the transistor voltage ratings.

Future Improvements

While the current revision serves as a highly successful proof of concept, several areas are targeted for future improvement:

• Regulator Tuning: The observed voltage drop under load is due to the implementation of a pure Proportional (P) regulator. A PI regulator caused stability issues in this revision, but with proper parameter tuning, stable operation with minimal offset drop is achievable.
• Ringing Attenuation: Adding a snubber circuit or increasing gate resistor values will dampen the switching node ringing. Alternatively, transistors with higher voltage ratings could be used, though at a slight cost to Rds(on) and gate capacitance.
• Component Optimization: The passive components and MOSFETs were intentionally over-provisioned for this prototype. A production-ready version would undergo stricter component selection to reduce costs.
• Software Hardening: The firmware requires further refinement and exhaustive safety testing to handle edge cases gracefully (e.g., during testing, one phase shut down, and the converter was ultimately saved by the external PSU's overcurrent protection).

Documentation

Comprehensive project documentation is available in the repository (written in Polish, prepared for university coursework in Power Electronics and Digital Signal Controllers):

• Raport Techniczny: Initial project considerations and mathematical foundations.
• Raport Implementacyjny: Simulated testing and core code fragments.
• Raport Wdrożeniowy: Physical implementation and final hardware measurements.
• Raport Projektowy: Executive summary of the project lifecycle.