Imported from GitHub: daglem/reDIP-RIOT · commit 8ac1335 · license CERN-OHL-S-2.0

Description

MOS 6530 RRIOT / MOS 6532 RIOT replacement

README

reDIP RIOT

MOS 6530 RRIOT / MOS 6532 RIOT FPGA replacement

Overview

The reDIP RIOT is an open source FPGA board which combines the following in a DIP-40 size package:

• Lattice iCE40UP5K FPGA
• 1Mbit FLASH
• 5V tolerant I/O

The reDIP RIOT provides an open source hardware platform for 6530 RRIOT / MOS 6532 RIOT replacements.

Designs for the iCE40UP5K FPGA can be processed by yosys and nextpnr.

I/O interfaces

DIP-40 header pins:

• 5V input
• 35 FPGA GPIO
• 3 FPGA open-drain I/O
• GND

All FPGA header I/O is 5V tolerant, and can drive 5V TTL.

SPI / programming header:

A separate header footprint is provided for (Q)SPI flash programming, with pinout borrowed from the iCEBreaker Bitsy.

Board Front

Board Back