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A custom FPGA-based VGA controller designed for 640×480 @ 60 Hz, implementing VGA timing generation, pixel logic and a 4-layer PCB using the Lattice iCE40HX1K FPGA.
This project implements a minimal yet fully functional VGA video controller without using vendor IP cores. The design follows a complete hardware development flow, starting from logic validation and RTL simulation to a manufacturable multilayer PCB.
The controller generates standard VGA sync signals and RGB video output compatible with conventional VGA displays.
The system is divided into three main functional blocks:
Initial VGA timing was verified using Digital simulation software to confirm counter behavior, sync pulse timing and active display window alignment.
Reference: Digital
The design is implemented in SystemVerilog using a modular structure:
vga_timing.sv – VGA timing and sync generationvga_pixel_gen.sv – RGB pixel generationvga_timing_tb.sv – Testbench for waveform-level verificationReferences:
RTLSimulation & WaveformA complete 4-layer PCB was designed in KiCad to host the VGA controller.
Layer stackup:
Key hardware features:
References:
ice40-vga-controller/ ├── digital/ # VGA timing validation using Digital simulation tool ├── systemverilog/ │ ├── rtl/ # SystemVerilog RTL source files │ └── sim/ # Testbench and simulation files ├── kicad/ │ ├── schematic/ # Circuit schematics │ ├── pcb/ # PCB layout files │ └── gerber/ # Manufacturing Gerber files └── README.md
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