Check a board before you order it

Start with the board's own rules

Open a project and pick the Checks tab. The default run is the board's own rules: the DRC constraints saved in KiCad Board Setup, plus schematic ERC. It tells you whether the design is self-consistent on its own terms.

It is not identical to pressing DRC in KiCad. Two things the desktop dialog does by default are not done here: it tests the board against the schematic (footprint and net parity), and it refills copper zones first. So a footprint swapped in the schematic and never updated on the board is exactly the kind of mistake this run will not find. Run DRC in KiCad with parity on before you order, and treat this as the check that runs for every reader of the page rather than as a replacement for the one on your own machine.

DRC and ERC read different files, and one failing does not drag the other down: the second still runs, so you can get a geometry result with no electrical result or the reverse. That holds whether the tool rejected the file or the stage ran out of time on a dense board. What you need at least one of is a result. If neither stage produced a report and one of them failed, the run is marked failed rather than served as an empty pass, so you never get a blank panel that reads like a clean board. Either way there is no silent gap: a check that produced nothing is reported as not run. A project with no PCB has nothing to run DRC against, and one with no schematic has nothing to run ERC against. The counts come first in the panel and the coverage note sits under them, so read past the numbers before you trust them.

One gap is worth knowing about because it is invisible by design, and because it survives into the fab check below. Rules the board's author set to Ignore in Board Setup stay ignored on both lanes. The worker honours the file rather than overriding it, so a rule someone switched off years ago cannot produce a violation no matter how badly the board breaks it. This is not theoretical: a board with unconnected items set to Ignore will render as clear for a fabricator while its nets are unrouted. Both lanes list the waived rules alongside the verdict for exactly this reason, so read that list. Inheriting a project you did not draw is when it bites, so open Board Setup and look at what is set to Ignore.

Then run it against a fab

Board Setup rules are whatever the designer typed. They are often looser than the shop that will build the board, and sometimes tighter, which costs money for no reason. The vendor profiles re-run DRC against a real fabricator's published limits:

• JLCPCB, 2-layer and 4-layer, 1 oz copper
• PCBWay standard, 1 oz copper
• OSH Park, 2-layer, 4-layer and 6-layer

You pick the vendor, not the profile. The layer variant is chosen for you from the copper layer count in the board itself, so a 4-layer design checked against OSH Park is graded against the OSH Park 4-layer numbers without you selecting them. If a vendor publishes no profile for your layer count, the run says so rather than falling back to a near miss.

Between them the profiles cover minimum track width, minimum clearance, annular ring, drill and hole size range, via diameter, copper to board edge, and hole to hole spacing. Which of those a given profile carries varies, because each one holds what that fab publishes rather than a common template. Via diameter is checked on the OSH Park profiles only. Copper to board edge is checked on JLCPCB and PCBWay only. Inner-layer track and clearance limits appear wherever the fab publishes them, which is not the same as wherever the board has inner layers: the single PCBWay profile covers 2 and 4 layers and carries inner-layer values either way. The panel lists the rules it applied, so read that list rather than assuming a rule ran.

Layer count changes the verdict, and not in the direction most people assume. A fab's multilayer line is often a finer process than its 2-layer line, so the 4-layer numbers are tighter tolerances the shop will accept rather than a stricter bar you have to clear. JLCPCB allows 0.09 mm track and clearance on 4-layer against 0.1 mm on 2-layer, and a 0.15 mm annular ring against 0.18 mm, on every layer rather than only the inner ones. So the same geometry can pass as a 4-layer board and fail as a 2-layer one, which is worth knowing before you drop a layer count late to save money.

Two things that change the result

The vendor lane refills copper zones before it runs. KiCad stores whatever fill was last saved to the file, and plenty of projects were committed without a refill, especially ones imported from GitHub. A stale fill changes clearance, isolated copper and thermal relief, so grading the saved fill would grade a board nobody is going to build. The board's-own-rules run does not refill, so it reports against the fill as committed. If the two lanes disagree with each other, or with your local run, that difference is the first thing to check.

Vendor profiles need a KiCad source project. On a board converted from another EDA tool you can still pick a vendor, but there is no button to run one: the panel explains why instead of producing a verdict, because conversion is lossy and a fab pass or fail computed on converted geometry would be worse than no answer. The board's-own-rules DRC still runs on a converted project; treat it as indicative and confirm anything that matters in the original tool.

Running a check needs you to be signed in. Reading a result someone already ran does not, so a reviewer opening your link sees whatever has been run, and cannot trigger a fresh run without an account.

What none of this catches

Everything above is geometry, plus connectivity within each file. It does not compare the board against the schematic, so a footprint changed on one side and not the other, or a net that only exists in one of them, passes. It does not know what your circuit is for either: it will not tell you the regulator is undersized, the footprint is mirrored, the connector is the wrong gender, the stackup does not give you the impedance you assumed, or that you have swapped SDA and SCL. It checks that the board can be built, not that it should be.

Before you pay: open the schematic and read it, check every footprint against the part you are actually buying, look at the 3D view for parts that collide or hang off the edge, and have someone else look at the power section. The library is full of boards that passed DRC and still needed a rework wire.

Sharing a board for review

Check results live on the project page, so sending someone the link sends them the findings too. If the design is not ready to be public, see sharing a board privately.