Upload an NROM homebrew ROM from a phone, load it into SRAM, and run it on a Japanese Famicom. No EPROM programmer, cartridge swapping, or battery-backed memory.
The native 60-pin Famicom Rev A-FC is the primary design. A frozen 72-pin NES-001 predecessor is preserved under experimental/nes/ for comparison and further development; it is not part of the FC manufacturing release. A separately isolated ESP32-S3 two-bank Mapper-3 experiment records the post-release bodge wiring, firmware, tests, and limited bench evidence without changing the stable NROM release.
[!WARNING]
Rev A-FC has a fabrication-complete design and build-tested firmware, but the assembled hardware has not completed bench validation. Do not insert an untested board into a Famicom. The 10 mm taller PCB also needs a custom shell; original cartridge-shell compatibility is not claimed.
What it does
The ESP32-S3 creates a Wi-Fi access point and browser upload page.
An uploaded mapper-0 .nes image is CRC-checked and committed to one of two flash slots.
At power-up, the ESP32 isolates the console bus, copies PRG and CHR data into SRAM, and verifies every byte.
The bus changes to RUN ownership and the blue LED becomes solid.
Press the Famicom console's red RESET button to start the game.
Unlike the front-loader NES, the Famicom has no CIC lockout circuit. The cartridge therefore cannot automatically hold and release console reset; the explicit RESET press is part of the Rev A-FC user flow.
74LVC245 isolation with fail-safe LOAD/RUN defaults
PCB
6 layers, 90.0 × 66.8 mm envelope, 1.2 mm, 60 gold fingers
Audio
Famicom sound loop through fitted 0 Ω R20
Power/debug
Console 5 V plus USB-C bench power and native USB flashing
The board keeps the standard-width tongue, connector datum, notches, centre slot, and 1.2 mm mating thickness. Only the edge opposite the fingers is extended by 10 mm for routing space.
“0 opens” is not treated as completion by itself. The release also requires classified DRC, power continuity, reference-plane checks, silkscreen review, CPL registration, and visual inspection.
The default development access-point password is vomit-roms. Change it through menuconfig before using the cartridge in a shared or public environment.
Hardware
Open hardware/nescart-fc.kicad_pro in KiCad 10. The checked-in PCB is the exact revision used to create the public manufacturing package.
The schematic is generator-backed:
python hardware/tools/gen_sch.py
Edit the netlist tables in gen_sch.py; do not hand-edit generated connectivity in the .kicad_sch files. See hardware/README.md before regenerating anything.
top and bottom manufacturing views and paste-stencil preview;
a SHA-256 manifest checked in CI.
These files are published for review and reproducibility, not as a recommendation to order an unvalidated board unchanged. Read manufacturing notes and the bench bring-up gate first.
Experimental NES variant
experimental/nes/ preserves the earlier 72-pin front-loader NES-001 design. It uses an ATtiny CIC clone to hold the console in reset while the ESP32 loads SRAM, which is materially different from the manual-reset FC flow. The snapshot passed its recorded schematic and PCB checks, but its assembly-placement gate and hardware validation are incomplete, so it is intentionally not fabrication-ready.
Experimental Mapper 3 modification
experimental/mapper3-esp32/ documents an
ESP32-S3-only, two-bank CNROM modification applied to one assembled Rev A-FC
board. It adds no new processor: a core-1 IRAM polling loop observes CPU D0 and
the existing decoded control signals, then drives CHR SRAM A13 through GPIO36.
Host tests, the ESP32 build, Mapper-0 regression, and one two-bank Mapper-3
target passed their recorded checks. Electrical margin, worst-case timing,
long-run Wi-Fi stress, and multi-board repeatability remain USER_REVIEW.
This is a reproducible experiment, not a revised manufacturing release.
Repository map
hardware/ KiCad 10 release source, libraries, models and core generators
firmware/ ESP-IDF / PlatformIO loader firmware and host tests
manufacturing/rev-a-fc/ sanitized Gerber, BOM, CPL, evidence and hashes
experimental/nes/ frozen 72-pin NES-001 design snapshot (not released)
experimental/mapper3-esp32/ post-release two-bank CNROM bodge and firmware
docs/ architecture, bring-up, manufacturing and licensing notes
scripts/ repository and release-integrity checks
This is a dual-licensed repository. Software and original general documentation are MIT. KiCad hardware design files, manufacturing artifacts, and designated visual/model assets are CC BY-SA 4.0; see the exact scope and attributions.
Connector behavior and dimensional research reference the community-maintained NESdev Wiki and the NES/Famicom cartridge dimensions project. The SRAM STEP model is from KiCad Packages3D and retains its upstream license and exception.
Famicom and Nintendo are trademarks of Nintendo. This independent project is not affiliated with or endorsed by Nintendo. Use homebrew software you have the right to run.
No comments yet. Be the first to ask about this board.
No comments yet. Be the first to ask about this board.