Imported from GitHub: Stanlazy/7z010_ddr · commit 335b6ad · license GPL-3.0

Description

4-Layer XC7Z010 DDR3 Layout

README

4-Layer XC7Z010 DDR3 Layout

A compact layout of XC7Z010 with DDR3.

Tested with DDR3L-1066 on PCB manufactured by JLC.

Traces are length matched to ±0.5mm with board thickness of 1.2mm

Package delay's equivalent length are calculated with dielectric constant of 4.05.

Traces are cutting reference plane? It works.™