UPduino-v3.0 and 3.1

Image credit: Gregory Benjamin

UPDuino v3.1: PCB Design Files, Designs, Documentation

The UPDuino v3.1 is a small, low cost FPGA board. The board features an on-board FPGA programmer, flash and LED with all FPGA pins brought out to easy to use 0.1" header pins for fast prototyping.

The tinyVision.ai UPduino v3.x Board Features:

• Lattice UltraPlus ICE40UP5K FPGA with 5.3K LUTs, 1Mb SPRAM, 120Kb DPRAM, 8 Multipliers
• FTDI FT232H USB to SPI Device
• ALL 32 FPGA GPIO on 0.1” headers
• 4MB SPI Flash
• RGB LED
• On board 3.3V and 1.2V Regulators, can supply 3.3V to your project
• Open source schematic and layout using KiCAD design tools
• Integrated into the open source APIO toolchain
• Works with IceStudio^{nightly/dev branch only at the moment}

Please see the wiki page for the changes that were implemented from v2.1. Some salient features are:

• 4 layer board with a solid ground plane, proper layout/decoupling for good signal integrity and FPGA operation
• Access to on-board 12MHz oscillator using a jumper
• All FPGA pins including LED driver pins are brought to 0.1" headers
• qSPI Flash capable
• tinyFPGA bootloader compatible

Here are some resources for you:

• Documentation (beyond what's on this GitHub)
• Discord channel
• Schematic
• AssemblyDrawing
• Blinking LED

TinyVision.ai blog posts:

• Magic Smoke and PTC's
• Lattice Modelsim on Windows
• Ground trampolines and Phase Locked Loops

You can buy this board here: US and non-EU orders: .

EU Orders with VAT paid:

For expedited shipping options, please visit the storefront at www.tinyvision.ai or email us directly at: sales at tinyvision dot ai.

Useful links

• Digi-Key Intro to FPGA Video series
• osresearch: large collection of very useful code and a good overview.
• UPduino FPGA tutorial using APIO
• A very detailed blog on implementing a RISCV in the FPGA
• Lattice iCECube2 tutorial
• Open FPGA verilog Tutorial

The next generation of Upduino (coming soon)

• pico-ice