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The front panel control strip for the XEBook Atari 8-bit laptop build: five tactile buttons on one panel-mount board.
Despite the repository name, this is not a FujiNet-only board. It serves two separate boards over two separate cables:
VOL_BUTTS on the XEBook PSU board, driving the PAM8407
amplifier's up/down volume controlJ_BTN1 on
FN32ROV-XEBook-KiCad, which mounts
the FujiNet FN32ROV WiFi/SIO adapter permanently inside the laptopOn the FujiNet main board those three buttons were moved off-PCB onto cable pigtails so
they could be panel-mounted (see that project's CLAUDE.md, "External button bar interface
(J_BTN1)"). This board is where they ended up, alongside the volume pair.
PinHeader_1x04_P2.00mm_Vertical, through-hole. Pin 1 = volume up,
pin 2 = GND, pin 3 = volume down, pin 4 = GND — matches the VOL_BUTTS connector on the
XEBook PSU pin-for-pin.PinHeader_1x04_P2.00mm_Vertical, through-hole. Pin 1 = GND, pin 2 =
swap, pin 3 = Bluetooth, pin 4 = reset — matches J_BTN1 on the main board pin-for-pin.Cable wires are soldered directly to both connectors' pins rather than using a mating connector.
fuji1 originally carried only the three FujiNet button signals with no dedicated ground pin — those buttons' return path only worked because it shared a ground reference with the volume cable. It is now a proper 4-pin header with its own GND pin, matching the main board's J_BTN1 so the two boards' cabling maps 1:1.
vol1 was a 3-pin header (GND / up / down), but the PSU's VOL_BUTTS connector it
plugs into is a 4-pin JST-PH with two grounds interleaved between the two signals. vol1 is
now 4-pin and matches VOL_BUTTS slot-for-slot, so that cable is a straight 1:1 harness
too. Note that pins 1 and 2 swapped roles in the process, so an existing 3-wire volume
cable cannot be reused on the new header.
See this repo's CLAUDE.md for the technical details of both fixes.
Previously fabricated with 3-pin connectors (see production/). Both 4-pin fixes are
designed, routed, and verified — kicad-cli sch erc and kicad-cli pcb drc --schematic-parity are clean (0 unconnected, 0 shorts, 0 parity issues) — and the
JLCPCB fab package in Fab/ is up to date. Not yet re-fabricated.
Built with KiCad 9. kicad-cli sch erc / kicad-cli pcb drc --schematic-parity are used
to verify the design.
CERN Open Hardware Licence Version 2 - Strongly Reciprocal (CERN-OHL-S-2.0), matching the main board.
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