An evidence-driven reference design for a compact dual brushed-DC motor driver for mobile robotics, combining electrical decisions, tolerance-aware calculations, BOM traceability, KiCad capture scaffolds, PCB/thermal rules, staged validation gates, and automated engineering checks.
Status: engineering reference with KiCad capture in progress, not a fabricated or bench-validated PCB. The electrical architecture, reference calculations and CAD handoff files are defined; verified schematic capture, footprint review, ERC/DRC, routing, fabrication and measured load/thermal results remain required before this can be called CAD-ready or hardware-validated.
Project snapshot
Reference device
TI DRV8848 dual H-bridge
Target use
Compact mobile-robot DC motor control
Engineering model
Current-limit tolerance, conduction loss, thermal screening, decoupling and interface checks
Engineering reference + CAD capture scaffold; no ERC/DRC/fabricated-board claim
Next proof milestone
Complete/verify schematic + footprints in KiCad, pass ERC, finish PCB placement/routing and pass DRC before fabrication outputs
Why this repository is different
Instead of presenting a generated schematic or board file as a “finished PCB,” this repository separates design intent, CAD capture, CAD readiness, fabrication readiness, and measured hardware validation. Critical assumptions live in YAML/CSV and are checked by code rather than being buried only in prose.
bring-up, validation, FMEA and manufacturing-release documentation
Reference design
Item
Reference target
Motor driver
TI DRV8848PWPR
Motor channels
2 brushed DC
Application VM
6–12.6 V
Expected continuous load
0.75 A/channel
Current regulation
0.56 Ω sense resistor/channel, VREF tied to VINT
Nominal modeled current limit
~0.893 A/channel
Modeled tolerance range
~0.838–0.948 A/channel
PWM target
20 kHz
VM local decoupling
0.1 µF + 22 µF / 25 V
VINT bypass
2.2 µF
Reference PCB
2 layer, 2 oz copper, ground plane, exposed-pad thermal vias
These are reference design targets, not measured specifications.
Architecture
flowchart LR
SRC[Battery / DC source] --> P[Protection front end]
P --> C[Local + bulk decoupling]
C --> D[DRV8848 dual H-bridge]
MCU[MCU] -->|AIN1/AIN2/BIN1/BIN2| D
MCU -->|nSLEEP| D
D -->|nFAULT| MCU
D --> A[Motor A]
D --> B[Motor B]
D --> SA[0.56 Ω sense A]
D --> SB[0.56 Ω sense B]
Those failures are intentional. They prevent the presence of generated KiCad source from being mistaken for verified footprints, ERC, DRC or Gerber review.
Engineering model
The main sizing utility evaluates the reference YAML against the DRV8848 profile. It checks application voltage, PWM frequency, nominal and tolerance-aware current limits, sense-resistor loading, local decoupling, and a deliberately simple junction-temperature screen.
The thermal result uses datasheet θJA as a screening calculation only. Actual junction/board temperature depends on PCB copper, exposed-pad soldering, via construction, airflow, enclosure and operating waveform, so hardware thermal testing remains mandatory.
Current regulation. The reference uses a 0.56 Ω sense resistor per channel with VREF tied to VINT. The connectivity contract models U1.VINT, U1.VREF, the VINT capacitor and exposed header reference as one physical rail. The model includes VINT and resistor tolerance rather than trusting only a nominal current-limit number.
Thermal strategy. The exposed pad, ground plane and thermal vias are part of the electrical design, not optional cosmetics. Rough thermal math is used to catch obviously bad choices early, then real hardware measurements must replace estimates.
Protection stays application-specific. Fuse, reverse-polarity device, TVS and optional bulk capacitance cannot be selected credibly without the final battery/source, cable/harness and motor transient behavior. The repo documents the architecture and review criteria instead of inventing part numbers.
CAD honesty. KiCad-native source now exists as an explicitly unvalidated capture scaffold. hardware/cad/netlist_spec.yaml remains the authoritative connectivity contract while real symbols, footprints, ERC/DRC and layout evidence are completed. The repository does not turn validation flags green merely because files were generated.
Contributing
Contributions are welcome when they improve traceability, calculations, CAD evidence, validation, documentation, or test automation. Read CONTRIBUTING.md before opening a pull request.
Real hardware contributions should record board revision, supply, motor/load, instrumentation, ambient conditions and test method so results remain useful to others.
First-Article Fabrication Package & Ordering
The Rev-A board manufacturing package is compiled and ready for fab house submission:
Stage 5 (Load Sweep): 500 mA continuous resistive load $\to$ 1.0 A motor load $\to$ thermal logging.
Primary component sources
The reference profile is derived from Texas Instruments' DRV8848 product page and datasheet. Re-check the current datasheet revision and device lifecycle before a real procurement/fabrication release.
License
MIT — see LICENSE. Hardware documentation and calculations are provided without warranty; independently verify all electrical, thermal and safety assumptions for the actual application.
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